| 摘要 |
PURPOSE:To prevent such a case where the data is fetched and executed as an instruction in a data storing area by generating an interruption via a microprocessor only when an address is outputted from the data storing area via the microprocessor in a fetching state. CONSTITUTION:When a microprocessor 1 fetches an instruction, an address and a control signal showing a fetching cycle are outputted to a bus 12. The comparators 6 and 7 compare the output address with the head and end addresses of a data storing area stored in the data head/end address storing means 4 and 5 respectively. As a result, an interruption signal 11 is applied to the microprocessor 1 via an interruption means 9 only when an address is outputted from a data area of a RAM 3 via a logic output means 8. The microprocessor 1 confirms the output of the address of the data storing area and resets a reading means 10 to restart a fetching operation. Thus it is possible to prevent such a case where the data stored in the data storing area is fetched and executed as an instruction. |
