| 摘要 |
PURPOSE:To reduce the number of PLL loops to one and to suppress the increase of circuit scale by allocating right and left pictures to the display of 4:2 interlace scanning when displaying a stereoscopic picture. CONSTITUTION:Right and left camera signals are respectively inputted to double speed converters 1 and 2 by a clock CKi and read out by an output clock CKo while changing the speed double. Corresponding to a field on the display dise, the signals are displayed while being changed over by a switch SW. A synchronizing signal on a camera side is inputted to a PLL circuit 3 and a clock CK synchronized with the horizontal synchronizing signal of a camera and horizontal and vertical synchronizing signals for 120MHz 4:2 interlace are outputted. The CK as the output of the PLL circuit 3 is used as the output clock CKo of the double speed converters 1 and 2 as it is and used as the input clock CKi while making the rate 1/2. Therefore, the input and output clocks can be generated by one PLL circuit 3. |
