发明名称 PSEUDO FAULT GENERATING MECHANISM FOR DATA PROCESSOR
摘要 PURPOSE:To produce a pseudo fault at an optional time point by setting the pseudo fault production timing to a timer and outputting a signal of a level in accordance with discrimination between a fixed fault and an intermittent fault from a valid signal holding circuit. CONSTITUTION:The type of a pseudo fault, the pseudo fault production timing, and the discrimination between the fixed and intermittent faults are set to an external device. This setting information is sent to a data processor and stored in a reception register 7 and an interruption is applied to a microprocessor 1. The microprocessor 1 sets the production timing of the pseudo fault to a timer 5 to start it and at the same time sets the value in accordance with the type of the pseudo fault to a pseudo fault register circuit 4. In addition, an FF 111 of a valid signal holding circuit 11 is set and reset in accordance with discrimination between the fixed and intermittent faults. When the timer 5 has a time-up state, a valid signal (a) is sent to the circuit 4 from a valid signal generating circuit 6 and a pseudo fault generating part 42 produces a pseudo fault in accordance with the value set at a register 41. Thus it is possible to produce the fixed and intermittent pseudo faults at each optional time point.
申请公布号 JPH03184133(A) 申请公布日期 1991.08.12
申请号 JP19890323222 申请日期 1989.12.13
申请人 NEC CORP 发明人 SUZUKI TSUNEO
分类号 G06F11/22 主分类号 G06F11/22
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