发明名称 VIDEO DISPLAY SYSTEM
摘要 <p>PURPOSE: To use a device in a system satisfying a high bit rate performance by adding a sequential serial access function to a MOS dynamic RAM. CONSTITUTION: A memory 5 has not only a serial port 2 but also a parallel port 6, and the port 6 is connected to a multiple address/data input/output bus 7 of a microcomputer 8. The memory 5 receives the address on the bus 7 to prescribe an address for the serial port 2 and prescribes also an address for memory read or write passing the parallel port 6. The memory 5 has a memory array 10 which consists of a matrix of memory cells and is divided in accordance with the size and form of a video display device 1 and the form of a selected memory. In this case, a circuit is provided which gives a first clock frequency for microprocessor and a second clock frequency which shifts video data from a register to a video signal input. Thus, a device suitable for a display system which has an improved resolution is obtained.</p>
申请公布号 JPH03184081(A) 申请公布日期 1991.08.12
申请号 JP19900210136 申请日期 1990.08.08
申请人 TEXAS INSTR INC <TI> 发明人 KEBIN SHII MATSUKUDONOUGU;DEBITSUDO SUMISU RAFUITSUTOU;JIYON EMU HIYUUZU
分类号 G06F12/00;G06F3/153;G06F12/04;G06F12/06;G06F19/00;G06T1/60;G09G5/00;G09G5/02;G09G5/36;G09G5/377;G09G5/39;G09G5/393;G09G5/395;G11C7/00;G11C11/401 主分类号 G06F12/00
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