| 摘要 |
<p>PURPOSE:To surely generate the set number of error bits by converting an error bit generating instruction synchronizing with a processor clock into the instruction synchronizing with a transmission line clock, and afterwards, generating an error bit setting pulse by delaying the instruction by two bits portion of the transmission line clock, and taking an exclusive OR with transmission line data. CONSTITUTION:Flip flops 21, 22 and a latch circuit 23 are the constituent part of a clock switching part 2, and the flip flops 31, 32, 34 and an EX-OR gate 33 are the constituent part of an error bit generating part 3. The error bit generating instruction synchronizing with the processor clock is converted into the instruction synchronizing with the transmission line clock by the clock switching part 2. Then, at the error bit generating part 3, after the error bit generating instruction synchronizing with the transmission line clock is delayed, and the error bit setting pulse is obtained, the check bits which are in-phase with a specified data bit are generated by the designated number of bits by taking the exclusive OR of this error bits setting pulse and the transmission line data, and are sent as the error bits. Thus, the set number of the error bits are surely generated.</p> |
