| 摘要 |
PURPOSE: To reduce power consumption by providing second suppression logic prohibiting a second clock signal for a register in response to address logic and a first clock signal in a logic circuit. CONSTITUTION: When an address line Ca is false, the matter that a first latch in the register is clock operated by a C clock signal is prevented by an AND gate 33. A control latch 34 is incorporated in the register also, and the state of the address line Ca is loaded in response to the real state in the C clock signal, and a data bit Al is loaded on a second latch 32 of an SRL array 36 in response to that a B clock signal 38 occurring while the delayed address line C'a is real is in the real state. The state of the delayed address line C'a is specified by the contents of the control latch, and when the delayed address latch C'a is false, the matter that the second latch in the register is clock operated by the B clock signal is prevented by the AND gate 35. Thus, the power consumption is reduced. |
