发明名称 Priority encoder.
摘要 <p>A priority encoder includes an encoder (20) for coding an input consisting of a plurality of bits, selectors (100 to 107), respectively provided for bit input terminals of the encoder, for respectively receiving corresponding ones of a plurality of bits of an operand input, each of the selectors including a switch circuit (1) to be controlled by an operand input bit, a carry line connected in series with the switch circuit and connected in series with all of the selectors, a first precharge circuit (3), connected to a carry line portion on one end side of the switch circuit, for precharging the carry line at a predetermined timing, a first detector (4) which is controlled by an enable signal for designating upper bit priority and detects whether a potential of a carry line portion on an upper bit side of the switch circuit is at a discharge level, a second detector (5) which is controlled by an enable signal for designating lower bit priority and detects whether a carry line portion on a lower bit side of the switch circuit is at a discharge level, and a third detector (6) for detecting whether one of outputs from the first and second detectors and the operand input bit are both in an active state. &lt;IMAGE&gt;</p>
申请公布号 EP0440221(A2) 申请公布日期 1991.08.07
申请号 EP19910101280 申请日期 1991.01.31
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIBA, MASUE, C/O INTELL.PROPERTY DIV.;NAKATA, SHIGEHARU, C/O INTELL.PROPERTY DIV.
分类号 H03M7/00;G06F7/74 主分类号 H03M7/00
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