发明名称 SEMICONDUCTOR CHIP PACKAGE
摘要 PURPOSE: To realize a rotational and linear symmetry by employing a pin-out construction for decreasing the surface area by stacking semiconductor chip packages. CONSTITUTION: Semiconductor chip packages P2 are abutting each other on the upper surface 28 and separated from each other on the bottom face 30 thereof. Pins 18, 20 on one P2 are connected with adjacent pins 20, 18 of the other P2 to constitute a module 26. The module 26 is provided with sixteen address input ends A0-A15 corresponding to those of P2 on the underside. The module 26 has write enable input ends WE0, WE1, output enable input ends OE0, OE1, eight select CS input ends CS0-CS3, i.e., input ends of four chips in the package 2 on the underside, and CS0 (upper side)-CS3 (upper side), i.e., the chip select inputs for four chips in the package 2 on the upper side. Pins are laid out such that the chip select and redundant pins are symmetrical to a line parallel with the pins. Consequently, a rotationally and linearly symmetric arrangement can be realized.
申请公布号 JPH03181163(A) 申请公布日期 1991.08.07
申请号 JP19900325100 申请日期 1990.11.27
申请人 INMOS LTD 发明人 ERUUIN POORU MAIKERU UEIKUFUIIRUDO;KURISUTOFUAA POORU HARUMU UOOKAA
分类号 H01L23/50;H01L25/10;H01L25/11;H01L25/18 主分类号 H01L23/50
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