| 摘要 |
PURPOSE:To execute a normal shift operation even when there is skew in a clock signal by inputting the first clock signal to the enable terminal of a first latch circuit while inverting the clock signal or not inverting it. CONSTITUTION:For a second latch circuit 1b, a data input terminal D2 is connected to an output terminal Q1 of a first latch circuit 1a. The output terminal of a control gate 8 is connected to an enable terminal EN of the second latch circuit 1b and first and second clock signals CK and SCK are inputted to two input terminals. The first clock signal CK is inputted to the enable terminal EN of the first latch circuit 1a while being inverted or not being inverted. In such a way, since the both latch circuits 1a and 1b are controlled by the first and second clock signals CK and SCK, the both latch circuits 1a and 1b can be simultaneously set in a holding state. Thus, even when there is slight skew in the clock signal, the normal shift operation can be executed. |
