Status register with asynchronous set and reset signals

摘要

A two stage binary status register is set and reset by independent signals and comprises a first stage flip-flop, the output of which is connected to a second stage latch circuit. The set signals and the reset signals are applied to the two stages in a manner which insures that the output of the second stage latch always supplies an output corresponding to each set input signal, irrespective of the times of arrival of the set and reset signals, including all conditions of signal overlap and simultaneous arrival of both the set and reset signals.