发明名称 PHASE LOCKED LOOP CONTROLLER
摘要 PURPOSE:To stabilize phase locked loop control by providing a first measuring means to measure phase difference between a frequency reference signal and an output pulse signal, and a second measuring means to measure the frequency change rate of the frequency reference signal, and controlling the output pulse signal corresponding to both measured results. CONSTITUTION:In an ordinary operation, such control is performed that the phase difference between an input signal f0 and an output signal f1 can go to zero with a microprocessor 23 and a preset counter 24 based on the phase difference output data of a first timer 21. When it is detected that the frequency change rate exceeds a prescribed value with the input frequency measured data of a second timer 22, such control that phase locked loop control for the input signal based on the output data of the first timer 21 is evaded and an output frequency before fluctuation can be held is performed. Thereby, the phase locked loop control without generating rapid change of the output frequency can be performed. Therefore, no rapid change of the output pulse signal occurs even when the frequency of the frequency reference signal changes steeply, and also, adjustment can be easily performed.
申请公布号 JPH03179918(A) 申请公布日期 1991.08.05
申请号 JP19890317860 申请日期 1989.12.08
申请人 TOSHIBA CORP 发明人 MIYAZAWA YOSHIAKI
分类号 H03L7/00 主分类号 H03L7/00
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