发明名称 PHASE OR AMPLITUDE DETECTOR AND PHASE LOCKED LOOP
摘要 PURPOSE: To remove the complexity of a layout related to a sine multiplier and to remove an impact having inferior odd harmonic by suitably switching capacitor type low pass filters(LPFs). CONSTITUTION: The system is provided with plural capacitor type LPFs SA to SD to be switched in response to an FM stereo composite signal including a 19kHz pilot signal and a clock generator for generating 1st and 2nd unoverlapped output clock signals. ϕ1, ϕ2 corresponding to multiples of twelve times of the 19kHz pilot signal. The system is also provided with means 12, 14 for supplying unoverlapped output clock signals to the LPFs SA to SD, CA so that positive and negative gains having the same absolute value are alternately generated when the inclination of the 19kHz pilot signal has the same polarity as a 57kHz pilot signal having the same phase or the reverse polarity in a zero gain period. Consequently, a full sine wave multiplier is not required, the complexity of a layout can be removed and an impact having inferior odd harmonic to be applied to the operation of the system can be removed.
申请公布号 JPH03179827(A) 申请公布日期 1991.08.05
申请号 JP19900215687 申请日期 1990.08.14
申请人 DERUKO ELECTRON CORP 发明人 RICHIYAADO ARUBAATO KENEDEII;GUREGORII JIYON MANRABU;JIEFURII JIYOSEFU MAARAA
分类号 H03K5/26;H03D1/22;H03L7/085;H04B1/16;H04H20/88 主分类号 H03K5/26
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