发明名称 MODULATOR USING PLL
摘要 PURPOSE:To attain the acceleration of the operation of a variable frequency divider and the simplification of configuration compared with the divider including a decimal point by varying the frequency division ratio of the variable frequency divider successively, and setting the reference frequency of a reference oscillator less than the prescribed channel interval frequency of a modulation circuit. CONSTITUTION:When the lock of a PLL circuit 15 is performed, the oscillation frequency f0 of a VCO 17 goes to N.fr (N: frequency division ratio). Therefore, the channel frequency of a modulation circuit 21 is varied with a prescribed band, for example, a prescribed channel interval frequency fch step in an European UHF TV channel by successively varying N. In the European UHF TV channel, the band of 30 channels (543.25MHz) to 39 channels (615.25MHz) is varied with a step of 7.99MHz less than the channel interval frequency fch=8MHz. Then, a signal to be modulated for TV receiver is obtained at the output terminal OUT of the modulation circuit 21 by performing the amplitude modulation of the desired oscillation output of the VCO 17 with a modulation signal.
申请公布号 JPH03179929(A) 申请公布日期 1991.08.05
申请号 JP19890317590 申请日期 1989.12.08
申请人 SONY CORP 发明人 ISHIKAWA NOBUYUKI;NARAHARA HISAAKI
分类号 H03L7/06;H03C3/00;H04B1/04;H04N5/40 主分类号 H03L7/06
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