发明名称 |
Interface controller module |
摘要 |
It consists of a coder, a decoder, an error checker, a loop test module and a PLL, incorporating a digital PLL specifically designed for matching the external data interface module to the internal data interface module in the Tesys B packet-switching system, being capable of supporting digital interfaces at the binary speed of 64 kbit/s.
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申请公布号 |
ES2020384(A6) |
申请公布日期 |
1991.08.01 |
申请号 |
ES19900000051 |
申请日期 |
1990.01.09 |
申请人 |
TELEFONICA DE ESPANA, S.A |
发明人 |
LIZCANO MARTIN PEDRO;CALVO TORRE FERMIN;CALVO TORRE FERMIN |
分类号 |
H04L12/56;H04L29/10;(IPC1-7):H04L29/10 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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