| 摘要 |
<p>A data processing system (10) is provided having a secondary cache (34) for performing a deferred cache load. The data processing system (10) has a pipelined integer unit (12) which uses an instruction prefetch unit (IPU) (12). The (IPU) (12) issues prefetch requests to a cache controller (22) and transfers a prefetch address to a cache address memory management unit (CAMMU) (24), for translation into a corresponding physical address. The physical address is compared with the indexed entries in a primary cache (26), and compared with the physical address corresponding to the single cache line stored in the secondary cache (34). When a prefetch miss occurs in both the primary (26) and the secondary cache (34), the cache controller (22) issues a bus transfer request to retrieve the requested cache line from an external memory (20). While a bus controller (16) performs the bus transfer, the cache controller (22) loads the primary cache (26) with the cache line currently stored in the secondary cache (34). <IMAGE></p> |
