| 摘要 |
To the respective drains of a pair of FET's which constitute an input stage differential amplifier circuit are cascade-connected a first transistor and a second transistor, respectively, whose bases are connected in common. To a pair of active elements of the next stage amplifier circuit is connected a detecting circuit for detecting the sum of the driving currents of these active elements. By the output of detection of the detecting circuit, the potential of the common base of the first and second transistors is controlled, so that the currents flowing through these first and second transistors are held constant, whereby the apparent load, for input signals, of the paired FET's is elevated.
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