| 摘要 |
<p>A delay circuit (14) of the type having current tree (60) for selectively applying a current source (66) to either a first (62) or a second (64) circuit node in response to the state of an input signal (Vin), the circuit nodes being resistively coupled (76, 78) to a first voltage source (Vdd) and providing an output signal (V3, V4) delayed from the input signal according to a delay response, the delay circuit being characterized by: a first capacitance circuit (102, 108, 120) coupled between a second variable magnitude voltage source (Vc) and the first circuit node; and a second capacitance circuit (100, 104, 118) coupled between the second variable magnitude voltage source and the second circuit node, the capacitances of the first and second capacitance circuits varying according to the magnitude of the second variable magnitude voltage source, the first and second capacitance circuits determining the delay response for the delay circuit.</p> |
