LATCH-UP PREVENTION IN A TWO SUPPLIES, CMOS INTEGRATED CIRCUIT BY MEANS OF A SINGLE INTEGRATED MOS TRANSISTOR

摘要

Latch-up in two supplies (+VCC and -VBB) CMOS integrated circuits is prevented by means of a single integrated protection MOS transistor, N-channel for P-Well CMOS or P-channel for N-Well CMOS, having its drain (source) connected to ground and its body region, gate and source (drain) connected to -VBB (+VCC). The desired threshold voltage and dimensions of the protection transistor do not present particular problems of implementation.