| 摘要 |
PCT No. PCT/DE88/00195 Sec. 371 Date Nov. 6, 1989 Sec. 102(e) Date Nov. 6, 1989 PCT Filed Mar. 25, 1988 PCT Pub. No. WO88/09037 PCT Pub. Date Nov. 17, 1988.A CMOS-RAM memory is composed of at least one main memory area SF whose memory cells are realized with a seven transistor basic cell (SC) in a gate array arrangement. The memory cells are thereby arranged in a matrix in the main memory area. A word line decoder (WD) lies at one side of the main memory area (SF) of the gate array arrangement in row direction, this word line decoder (WD) containing - per row of memory cells-a decoder sub-circuit (WDT) realized with basic cells for generating a word line signal from address signals. A drive circuit (AST) is arranged between the word line decoder (WD) and the main memory area (SF), the drive circuit (AST) providing - per row of memory cells - a drive sub-circuit (ASTT) for generating a write signal in inverted and non-inverted form from the word line signal and from a selection signal with which the memory cells of a row of memory cells are driven. The write/read circuits realized in basic cells are arranged at another side of the main memory area, the information being capable of being written into the main memory area or, respectively, information being capable of being read out of the main memory area via these write/read circuits. The RAM memory has the advantage that the capacity of the memory on the gate array arrangement can be adapted to the requirements without difficulty.
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