发明名称 PHASE LOCKED LOOP
摘要 PURPOSE:To reduce the chip size of an IC by constituting the phase locked loop of plural VCOs having respectively different voltage-frequency conversion coefficients and a selector circuit for selecting the outputs of plural VCOs. CONSTITUTION:A VCO 3 having a larger Kv inputs the output 8 of an LPF 2, executes the voltage frequency conversion of the input and outputs the converted result. When the input signal of read data 6 is included in a sink area, the selector circuit 5 selects the output 9 of the VCO 3 having the larger Kv to allow the input to rapidly follow a reference clock. When the input signal of the read data 6 is in a data area, the circuit 5 selects the output 10 of a VCO 4 having a smaller Kv to allow the input to slowly follow the reference clock so as not to follow phase variation such as a peak shift.
申请公布号 JPH03175740(A) 申请公布日期 1991.07.30
申请号 JP19890315075 申请日期 1989.12.04
申请人 SEIKO EPSON CORP 发明人 OGAWA TAKAHISA
分类号 H03L7/107 主分类号 H03L7/107
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