| 摘要 |
A digital-to-analog (D/A) converter is disclosed for converting an n-bit digital signal represented by a 2's complement into an analog signal. The converter comprises a capacitor array comprising (n-1) capacitors each being weighted by a 2's power and commonly connected at one electrode to a common output terminal; control means for producing first, second and third control signals from an operation clock and the digital signal; and a switch array comprising (n-1) switches connected one-to-one to the other electrode of the (n-1) capacitors for applying either one of a first and a second reference voltage to the (n-1) capacitors in response to the second control signal. An additional capacitor is connected at one electrode to the output terminal while a first switch is connected to the other electrode of the additional capacitor for feeding either one of the first and second reference voltages to the additional capacitor in response to the first control signal. A second switch is connected to the output terminal for feeding the first reference voltage in response to the third control signal. |
