| 摘要 |
<p>PURPOSE:To simplify the circuit constitution by stopping the readout of an input data signal by a matching time corresponding to a period subtracting a specific period from a reference period of a timing pulse. CONSTITUTION:A input data D1 and an input timing pulse P1 are stored tentatively in a first-in first-out buffer memory (FIFO memory) 1 by a write clock WR. When a reference pulse PR and a readout pulse are not matched, a period from the reference pulse PR till the time when a timing signal P3 is outputted from the FIFO memory 1 is counted by using a counter 3 and the counted period is subtracted from the reference period of the timing pulse and the readout of the FIFO memory 1 is stopped for the period (matching period). Thus, the timing matching circuit is constituted by only adding the counter and a simple circuit controlling the counter.</p> |
