| 摘要 |
In a frequency discriminator, a real part of complex-valued symbols which occurs at a first instant of the period of the symbols is equalized so that its intersymbol interference is minimized and an imaginary part of the symbols which occurs at the same first instant is likewise equalized to minimize its intersymbol interference. A real part of the symbols which occurs at a second instant of the period is equalized to minimize its intersymbol interference and an imaginary part of the symbols which occurs at the same second instant is equalized to minimize its intersymbol interference. The equalized first-instant real part is delayed by a first delay circuit by a time interval equal to the interval between the first and second instants, and the equalized first-instant imaginary part is likewise delayed by a second delay circuit. A first multiplier multiplies the output of the first delay circuit with the equalized second-instant imaginary part and a second multiplier multiplies the output of the second delay circuit with the equalized second-instant real part. The output of the second multiplier is subtracted from the output of the first multiplier to generate a signal representative of a frequency variation.
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