发明名称 LOGIC PATH LENGTH REDUCTION USING BOOLEAN MINIMIZATION
摘要 An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.
申请公布号 CA1287174(C) 申请公布日期 1991.07.30
申请号 CA19880580777 申请日期 1988.10.20
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 HATHAWAY, DAVID J.
分类号 G06F17/50 主分类号 G06F17/50
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