发明名称 PLL CIRCUIT
摘要 PURPOSE:To expand a frequency modulation characteristic to a low frequency and to enhance the response characteristic by decreasing the natural frequency of a PLL loop as time elapses in response to the pull-in operation of the PLL loop. CONSTITUTION:A PLL(Phase locked loop) circuit consists of a reference oscillator 1, a phase comparator 2, a loop filter 30, phase comparator output circuits 6l-6n, gate circuits 7l-7n and a selection control signal generating circuit 8. Then the natural frequency of the PLL loop is decreased as the time elapses from a prescribed value in response to the pull-in of the PLL loop. Thus, the frequency modulation characteristic is expanded up to a low frequency and the PLL circuit with the excellent response characteristic is obtained.
申请公布号 JPH03174816(A) 申请公布日期 1991.07.30
申请号 JP19890312274 申请日期 1989.12.02
申请人 TOSHIBA CORP 发明人 HORIE HIROSHI
分类号 H03L7/18;H03C3/00;H03L7/107 主分类号 H03L7/18
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