| 摘要 |
<p>PURPOSE:To reduce the number of changes in a mounting operation to a minimum and to shorten a designing time by a method wherein, when a delay time of a data path cannot be kept within a range of a permissible error which takes into consideration a difference between a standard value of a delay time of a clock path and the delay time of the clock path at a time when an element is arranged actually, the element is rearranged, the data path is again set between elements and the data path is judged. CONSTITUTION:A data path delay DATA refers to an actually obtained data path delay time (d) which has been decided by taking into consideration discrepancies X, Y between supposed clock-delay standard values N1, N2 and actual clock delays C1, C2. Thereby, the data path delay DATA which has been formed here takes into consideration a discrepancy of an interconnection of a clock system beforehand. A measuring operation is executed by using Formula I. When the path delay time DATA of a data system does not satisfy Formula I, the data system is redesigned. In the formula, gamma: cycle time of system clock.</p> |
