FSK digital data transmission over power supply networks - involves synchronised read-out of frequencies stored in microcontroller's memory with no time lag between sample values
摘要
Messages (13) and addresses (14) identifying their sources are digitised by a microcontroller or gate array (11) which controls (16) the power amplifier stage (27) feeding the power line (10) via a wideband coupler (29). The data and address sequence (15) passes through a D/A converter (21) and low-pass filter (23), which at each shift of frequency are deactivated (25) for the duration of a sampling interval. The memory is read cyclically by program branching in the microcontroller (11), synchronised by a zero-crossing detector (19). ADVANTAGE - Easily mass-produced transmitter allows reliable communication without cross-talk or undue interference from external sources.
申请公布号
DE4001266(A1)
申请公布日期
1991.07.25
申请号
DE19904001266
申请日期
1990.01.18
申请人
WALDSEE ELECTRONIC GMBH, 7967 BAD WALDSEE, DE
发明人
BAIER, PAUL WALTER, PROF. DR.-ING., 6750 KAISERSLAUTERN, DE;DOSTERT, KLAUS, DR.-ING., 6751 KRICKENBACH, DE