| 摘要 |
PURPOSE:To surely transmit data even in the case of the simultaneous occurrence of transmission requests in respective microprocessors by providing a third control line through which a signal to permit/inhibit data transmission from a master microprocessor to a slave microprocessor is sent. CONSTITUTION:The signal to permit/inhibit the data transmission from a master microprocessor 1 to a slave microprocessor 2 is outputted from the microprocessor 1 to the microprocessor 2; and if transmission data simultaneously occur in both microprocessors 1 and 2, the slave microprocessor 2 recognizes the signal as a transmission request signal regardless of the reception state of the master microprocessor 1 unless receiving the transmission permission signal and does not transmit data and is set to the data reception state. Consequently, data is transmitted from only the master microprocessor 1. Thus, data collision on a two-way data bus is avoided.
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