| 摘要 |
PURPOSE:To eliminate the initializing of buffer register and to attain the reduction of a load of a channel and high-speed processing, by performing error check as to only a prescribed byte unit data being indicated as effective with a byte mark. CONSTITUTION:A byte mark is written in a byte mark register BMR0 in correspondence to the byte location of a data buffer register DBR0 which has been written and the content of the BMR0 is shifted to a BMR1 in synchronizing with the shift from the DBR0 to the BMR1. To a storage controller SCU, a 4- byte data is transmitted from a DBR3 and the byte mark of 4 bits is transmitted from a BMR3, and the data in each byte is checked at parity checkers PC0-3. The logical product is taken by gates G0-G3 at each bit of the BMR3 and the result is given to a channel data check controlling section CDC, then it is not required to initialize the DBR0-3. |
