| 摘要 |
PURPOSE:To reset only the processed bit, by using the JK type FFs to plural registers connected to a memory bus to set or reset the register by a CPU with every bit. CONSTITUTION:Registers 101 and 102 of JK type FF which can be set or reset are connected to a memory bus 2 led from a memory access device 1. At the same time, a module 15 which is not synchronous with the device 1 and can set or reset the registers 101 and 102 is provided, and the contents of the register 101 or 102 to which a bit is set by a request signal given from the module 15 (picture recording control device) is read by the device 1 via a read data bus. A desired data process is carried out by the device 1 to the above-mentioned request signal. Thereafter, the register 101 or 102 which is reset via an address bus 3 is designated. Then only the bit that is set by the request signal of the register 101 or 102 is reset based on a table of truth of the JK type FF. Thus a process request is processed in an assured way. |
