发明名称 MULTIPLEXING SYSTEM OF DIGITAL SYNCHRONIZING CLOCK
摘要 PURPOSE:To supply a clock having high accuracy without instantaneous cutoff, by automatically executing phase synchronization between clocks and a changeover in the event of a fault, by plural input clocks. in a digial synchronizing clock multiplexing system for a digital switchboard. CONSTITUTION:Clock signals from a high-accuracy clock generator OSCO and OSCI are inputted to C0 and C1 terminals of an input selection controlling circuit O/ICONT 100, respectively, and are sent to a clock selector SEL400 through a phase synchronizing circuit PHSYC200 and 300. In PHSYCs 200, 300, in case when its own clock input is sent from the presently working system, the input to an H terminals is outputted as it is, and in case when it is sent from the st and-by system, a clock inputted to the H terminal is delayed, and a clock synchronizing with a clock of an M terminal is outputted. Accordingly, the clocks of the presently working system and the stand-by system are in an acquistition state of synchronism, and even if the clock of the presently working system is cut off, it is switched to a clock source of the stand-by system automatically without short break.
申请公布号 JPS57105017(A) 申请公布日期 1982.06.30
申请号 JP19800182517 申请日期 1980.12.23
申请人 NIPPON DENKI KK 发明人 HOSAKA TAKEMI;JINBOU TOORU
分类号 H04Q3/545;G06F1/04;H04M3/22;H04Q11/04 主分类号 H04Q3/545
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