发明名称 TEST FACILITATING CIRCUIT
摘要 PURPOSE:To enhance test efficiency by mounting an input/output means performing initial setting of the memory part within a first main module and reading the data from the memory part and a usual operation means usually operating a common bus control circuit and the memory part. CONSTITUTION:When TMOD is set at a level 1 through a test mode control wire lT and a test mode is set, usual operation is stopped. Next, the common bus control data to an instruction register (IR)1c through a test I/O control wire l1 is set. Subsequently, the address of the memory part 4a or 5a of a reading destination is written in an address register (AR)1d through the control wire l1. Next, SICLK is set at a level 1 through a usual operation control wire lS. By this constitution, the data of the memory part indicated by the address in the AR1d is read in a data register (DR)1e through a common bus 40. Finally, the data of the DR1e is read from the control wire l1.
申请公布号 JPH03167487(A) 申请公布日期 1991.07.19
申请号 JP19890306442 申请日期 1989.11.28
申请人 TOSHIBA CORP 发明人 YAGUCHI TOSHIYUKI
分类号 G01R31/28;G01R31/3185;G06F11/22;G11C29/00;G11C29/14;H01L21/66;H01L21/822;H01L27/04 主分类号 G01R31/28
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