发明名称 CLOCK GENERATING CIRCUIT
摘要 <p>PURPOSE:To adjust the clock frequency by constituting a ring oscillator formed by a gate circuit having a delay corresponding to a gate delay of a clitical path for determining an operation threshold in an IC, as a clock generating circuit in the IC, and controlling a power supply voltage of its oscillator. CONSTITUTION:A ring oscillator is constituted of a gate circuit having a delay corresponding to a gate delay time of a path in which a gate delay in an IC becomes maximum, that is, a clitical path. This ring oscillator is incorporated to the IC 5 as a clock generating circuit 6. In such a state, a frequency of a clock is adjusted due to a fact that a power supply voltage supplied to the ring oscillator is controlled. In such a way, the frequency of the clock can be adjusted, an optimal frequency can be selected, and a margin of a period of the clock against the date delay can be set to a necessary minimum and optimal state.</p>
申请公布号 JPH03166614(A) 申请公布日期 1991.07.18
申请号 JP19890306958 申请日期 1989.11.27
申请人 SONY CORP 发明人 IWASE SEIICHIRO
分类号 G06F1/04;G06F1/12 主分类号 G06F1/04
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