| 摘要 |
PURPOSE:To output a bit-synchronized clock stably at all times even if a digital input signal has an omission by providing an omission detecting means, etc., and setting the follow-up ability of a phase-locked loop(PLL) circuit high. CONSTITUTION:A digital input signal is supplied to the phase comparator 3, etc., of the PLL circuit 1 and the output of a voltage-controlled oscillator(VCO) 5 and the output of an omission detecting circuit 11 are supplied to a feedback clock converting circuit 12. Then the output of the VCO 5 which is bit- synchronized with the synchronizing signal of the input signal is outputted as a fundamental clock from the circuit 12 in a period wherein the synchronizing signal appears in the input signal, and if the synchronizing signal becomes absent, the fundamental clock of frequency nearly equal to the clock outputted by the VCO 5 is outputted. Namely, the output of the VCO 5 which is bit- synchronized with the synchronizing signal of the input signal from the circuit 12 is outputted as the fundamental clock at all times and the stable fundamental clock is fed back to the circuit 1, whose follow-up ability can be set high, thereby obtaining the bit-synchronized clock even if the input signal has an omission. |
