发明名称
摘要 PURPOSE:To execute the subtraction of an expanded input at the time of expansion only by a multiplier by dividing the expanded input into two high-order and low-order bits to process the expanded input. CONSTITUTION:In case of executing subtraction by using an nXn bit multiplier to expand an NXN (N>n) bits multipler, logic adding expansion inputs Mi, Mj independently as they are or after inversion by two inputs ADD/SUB, Kc is formed. The multiplier is constituted by adding logic 0 to Kc at the use of a unit, executing addition, i.e. directly inputting the Mi, Mj, when ADD/SUB=0, and executing subtraction, i.e. inverting and inputting the Mi, Mj when ADD/ SUB=1. Consequently, the Mi, Mj are added to products Xi, Yi directly or after inversion by the ADD/SUB and Kc values as shown in the figure.
申请公布号 JPH0345419(B2) 申请公布日期 1991.07.11
申请号 JP19830045467 申请日期 1983.03.18
申请人 NIPPON ELECTRIC CO 发明人 UMEKI YOSHITAKA
分类号 G06F7/53;G06F7/508;G06F7/52;G06F17/10 主分类号 G06F7/53
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