| 摘要 |
<p>A snubber circuit for a neutral clamped power inverter. The power inverter includes power transistors, a current sensor at the inverter output and a neutral clamping circuit connected between the inverter output and a neutral point in a DC power source which supplies the inverter. A controller circuit is connected to the current sensor, to the power transistors and to the neutral clamping circuit to selectively enable and disable the power transistors and the neutral clamping circuit in accordance with the inverter operation and current direction at the inverter output to minimize current transients at the load. Snubber circuits are provided to reduce output current variations, to reduce switching losses and to minimize the effects of parasitic inductances.</p> |
