发明名称 MEMORY CHECK SYSTEM
摘要 <p>PURPOSE:To detect the fault of a counter to generate a sequential load address signal in a control memory by working data so that the result of a parity check to the obliquely read data can be impossible, when the oblique read of the data is generated. CONSTITUTION:As respective pattern data, the data of an address 0 and the data of other all addresses 1-1023 are worked and when the oblique read of the data is generated between memories A and B, the data are used so that the result of the parity check to obtain an odd-number parity can be impossible. Thus, the cell stack of a memory cell itself in the memories A and B is detected and simultaneously with the detection, the fault of the internal counter, which generates the sequential load address to the memories A and B respectively, is detected as well.</p>
申请公布号 JPH03160538(A) 申请公布日期 1991.07.10
申请号 JP19890299737 申请日期 1989.11.20
申请人 FUJITSU LTD 发明人 SAKAI MASAKI;MURAYAMA MASAMI;KATO MIHARU
分类号 G06F12/16 主分类号 G06F12/16
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