发明名称 MONITORING SYSTEM FOR COMMON BUS
摘要 PURPOSE:To facilitate resetting a processing device, by monitoring the signal change on a prescribed signal line of a common bus to record the state of the bus for every change and by freezing the state recording when the signal change is not detected over a constant time. CONSTITUTION:A processing device CPU2, a bus monitoring device 3, a main storage device 4, and an input/output device 5 are connected to a common bus 1, and devices 2-5 communicate mutually through the common bus 1. Devices 2 and 3 are connected by a reinitial load indication line l1, a line l2 indicating the stop state, a line l3 indicating the check stop state, and a line l4 indicating the waiting state. The start and the end of an access on the common bus 1 are monitored by the device 3, and states at these time points are recorded; and if no change is detected over a constant time when the CPU2 is not in the stop state, the state recording of the common bus 1 is frozen, and the CPU2 is reset. By this operation, a processing program is loaded again from the external to the CPU2.
申请公布号 JPS57111718(A) 申请公布日期 1982.07.12
申请号 JP19800187789 申请日期 1980.12.29
申请人 FUJITSU KK 发明人 OZAWA HIDEKIYO
分类号 G06F11/30;G06F13/00;G06F13/362 主分类号 G06F11/30
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