| 摘要 |
To accelerate the image processing of binary images, hard-wired logic circuits are provided by means of which the image information items are processed line by line. For the segmentation, the image information items of adjacent lines are in each case transferred into one register each and are logically combined in a logic circuit so that pixels of a coherent object to be segmented are deleted in an image store and are transferred into a buffer store. To form segmentation seeds, hard-wired logic circuits and sequences are used. |
