| 摘要 |
<p>An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region. In the inventive process, the contact windows (303, 304, 302) are etched in the conformal dielectric (201) prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) (401) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows (302). <IMAGE></p> |
