发明名称 Sense amplifier circuit coupled to a bit line pair for increasing a difference in voltage level at an improved speed
摘要 A sense amplifier circuit is associated with at least one memory cell and comprises a series combination of a first p-channel type transistor and a second n-channel type transistor coupled between a source of positive voltage level and a first input node, a first negative feedback loop coupled between the first input node and the second n-channel type transistor, a series combination of a third p-channel type transistor and a fourth n-channel type transistor coupled between the source of positive voltage level and a second input node, a second negative feedback loop coupled between the second input node and the fourth n-channel type transistor, an output circuit coupled to the first and third n-channel type transistors in a current-mirror fashion and producing an output data signal, and first and second load elements respectively coupled between the first and second input nodes and a ground node, wherein each of the first and second load elements is smaller in conductance than the memory cell and restricts the associated input node to excessively fluctuate upon a change of memory cell to be accessed.
申请公布号 US5029138(A) 申请公布日期 1991.07.02
申请号 US19900566516 申请日期 1990.08.13
申请人 NEC CORPORATION 发明人 IWASHITA, SHINICHI
分类号 G11C17/18;G11C7/06;G11C16/28;G11C17/12 主分类号 G11C17/18
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