| 摘要 |
PURPOSE:To reduce the manhour for addition or extension of a 2-bit error receiving circuit to a host device when an error correction/collation ECC function is added to a memory part by reporting a 2-bit error to a central control part serving as a host device as a parity error via an ECC circuit. CONSTITUTION:When a 1-bit error is detected in the data read out of a memory part 11, an ECC circuit 12 corrects the error bit into a normal bit and sends it to a memory control part 13 via a data bus 21. If a 2-bit error is detected, the circuit 12 changes the data including the 2-bit error and inputted from the part 11 into the data that can be decided as a parity error by a memory control part 13. Then the changed data is sent to the part 13 via a data bus 21. Thus it is possible to reduce the manhour for addition or extension of a 2-bit error receiving circuit to a host device when an ECC function is added to the part 11. |
