| 摘要 |
A semiconductor memory apparatus of an internal synchronization type uses a clock signal generated by detecting a change in address or control signal as an internal synchronization signal. The apparatus includes a dummy memory cell for fixing data thereto in advance; a precharging circuit for precharging an internal memory cell and the dummy cell; a precharge completion detector for detecting the completion of the precharging operation when a dummy bit line from the dummy cell attains a predetermined voltage level by the precharging operation, the precharge completion detector transmitting a signal for completing the precharging operation with respect to the precharging circuit; and a device for reading or writing data through a bit line to the memory cell by the completion of the precharging operation by the precharge completion detector.
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