发明名称 CHIP CLOCK GENERATING SYSTEM
摘要 PURPOSE:To simplify the demodulation system equipment of an earth central station by detecting a slot timing from a frame signal included in a signal sent from the earth central station in each VSAT station (subminiature station) and generating a chip spread signal in a chip clock synchronously with the slot timing. CONSTITUTION:Each VSAT station 2 receives a signal sent to each VSAT station 2 via a communication satellite 3 from an earth central station 1, a frame detection section 21 detects a frame signal included in the signal and generates a slot timing signal CS synchronously with it. A chip clock generating circuit 22 receives the signal CS and generates a chip clock Cc synchronously with the CS. Upon the receipt of a packet signal SP sent to the earth central station 1, a chip spread signal generating section 23 generates the chip spread signal SC synchronously with the signal CC. A modulation section 24 receives the signal SC and modulates the carrier and sends the modulated signal to the earth central station. The earth central station 1 receives it via a communication satellite 3 to demodulate the signal synchronously with the transmission slot timing.
申请公布号 JPH03153130(A) 申请公布日期 1991.07.01
申请号 JP19890292702 申请日期 1989.11.09
申请人 NEC CORP 发明人 OTANI SUSUMU;IWASAKI HARUYA
分类号 H04J3/06;H04B7/212;H04L7/00 主分类号 H04J3/06
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