| 摘要 |
PURPOSE:To shorten the processing cycle of a central arithmetic processor without loosing the parallel arithmetic performance by adding a carry signal produced from an arithmetic process of a data arithmetic unit to the number of adders to be added via an increment device in order to obtain the address data. CONSTITUTION:In the register/indirect 8-bit displacement, an arithmetic and logic unit ALU 19 calculates the 8-bit displacement and the lower 8 bits of the data on a register W2. Then the carry signal obtained from the calculation is selected by a carry selection circuit 25. The circuit 25 sends the carry signal to a B increment/decrement device 52. On the other hand, the high-order data, etc., are transferred to the device 52 and a C increment/decrement device 53. Then the A-C increment devices 51-53 work after deciding the increment or the decrement of a constant 0 based on the code extension value. In a register indirect 16-bit displacement, the arithmetic result is supplied to a carry selection B circuit 26 and then sent to the device 53. Thus the addresses are calculated by the ALU 19 and the devices 51-53. Then the processing cycle is shortened while maintaining the parallel arithmetic performance. |
