发明名称 AUTO-DELAY GAIN CIRCUIT
摘要 <p>A multi-stage output buffer provides for inactivation and then delayed reactivation of a second gain stage (106) after a data transition. The delay imposed is a function of the output voltage, which is fed back through a threshold detector (110). A transition detector (112) is coupled to data inputs so that it can inactivate the second gain stage upon a data transition; the transition detector is coupled to the threshold detector so that it can activate the second gain stage once the output voltage crosses a predetermined threshold voltage. This configuration imposes relatively long delays on second gain stage activation when large loads are applied to keep switching transients to tolerable levels. When lesser loads are applied, a shorter delay permits more rapid throughput.</p>
申请公布号 WO1991009466(A1) 申请公布日期 1991.06.27
申请号 EP1990001813 申请日期 1990.10.23
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