| 摘要 |
A method of making a DRAM cell capable of increaisng storage capacity and for which is amendable to large-scale integration. The method provides a DRAM cell having stacked and trench capacitors and a transistor of second conductivity type opposite to a first conductivity type on a semiconductor substrate of the first conductivity type. Polycrystalline silicon of a cell node in the stack capacitor is coupled to source region of the transistor. The cell node of the trench capacitor is coupled to the source region of the transistor through an N-type diffusion region around the trench that is formed between said source region and a field oxide. Over the trench capacitor is disposed the stacked capacitor, and the cell nodes are coupled to each other. A cell plate filling the inside of the trench may be used in common since it surrounds the polycrystalline silicon, that is, the cell node of the stacked capacitor.
|
