| 摘要 |
The cache memory, consisted of SRAM (static random access memory) , has originally two approaches, i.e. physical address tagged cache virtual address tagged cache. More popular virtual address tagged cache has synonym problem of possible two virtual address for a information. Implementing both table lookaside buffer (TLB)(50) and address inverse translation cache (AITC) (60) memroy solves the synonym problem, which means the physical address is translated into the virtual address and vice versa. And system bus supervisor is an additional structure to the system bus, resulting consistent data flow in multi-processor system. Therefore this architecture solves access time gap between CPU memory and cache memroy rather than using flushing or PID (process ideatifien) in old system.
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