| 摘要 |
PURPOSE:To reduce chip size by forming a drive MIS transistor on the surface of monocrystalline silicon substrate and a load MIS transistor and a transmission MIS transistor on the surface of the substrate by way of an insulation film. CONSTITUTION:A channel section of transmission N channel MIS transistors Q3 and Q4 is not installed on the surface of a P<-> type single crystal silicon substrate but installed on P<-> type polycrystalline silicon thin film layers 116 and 117 in the fifth layer formed on drive N channel MIS transistors Q1 and Q2 or load P channel MIS transistors R1 and R2 by way of an insulation layer. This construction makes it possible to eliminate the need for an area required to install the transmission N channel MIS transistors Q3 and Q4 and hence reduce the chip size. |
