| 摘要 |
PURPOSE:To eliminate the generation of error performance induced by a parasitic MI transistor by forming an interlaminar insulation film which interfaces with the channel section of a load MIS transistor and a transmission transistor so that it may be thicker than a gate insulation film between the load MIS transistor and the transmission MIS transistor. CONSTITUTION:Transmission MIS transistors Q3 and Q4 are installed on load MIS transistors R1 and R2 by way of a first insulation film 152. A part of the insulation film 152 which interfaces with the channel section of R1 and R2 or Q3 and Q4 is formed so that its film thickness may be greater than that of gate insulation films 150 and 151 of R1 and R2 or Q3 and Q4. A bit line paired metal interconnection layer 120 is installed to Q3 and Q4 by way of a second insulation film 154. At the same time, a part of the second insulation film 154 which interfaces with the channel section of Q3 and Q4 is formed so that its film thickness may be greater than that of a gate insulation film 153 of Q3 and Q4. This construction makes is possible to eliminate the generation of error performance induced by a parasitic MIS transistor. |
